AST RESEARCH, INC.        TECHNICAL BULLETIN # 1515           6-11-96 
 
 
 
TITLE: Manhattan DIMM Sizes Cannot Be Mixed  
 
 
SUMMARY 
 
   DIMM Memory of differing sizes cannot be mixed in the Manhattan  
   S/6200 or Manhattan Commerce Pro servers.  This limitation is due  
   to an errata in the Intel 82450GX chipset used in Manhattan Pentium 
   Pro servers.  Mixing DIMMs may result in lost or corrupted data. 
 
   Valid memory configurations are comprised of either all 16MB or  
   all 32MB DIMMs. 
 
   A detailed explanation of this issue is provided below. 
 
   This issue applies to the following systems: 501832 and 503076 
 
 
ISSUE 
 
   This erratum can only occur if: 
 
   * Interleave increments containing 8MB or 32MB of memory exist in  
     conjunction with interleave increments which contain other amounts 
     of memory, or 
 
   * One or more interleave increments have 8 or 32MB of memory, and  
     there are no DRAM modules in the first row (row 0) of the memory  
     subsystem. 
 
   In systems which support two or more rows of memory (other than  
   systems which support two rows of double-sided SIMM DRAM only), one 
   must be careful not to mix DRAM of certain sizes.  If there are 8 or 
   32MB of DRAM in any interleave increment, all other interleave  
   increments must have the same amount of DRAM, and row 0 must be  
   populated with DRAM modules to avoid data corruption due to this 
   erratum. 


BACKGROUND 
 
   DRAM (Dynamic Random Access Memory) is addressed using addresses  
   defined by rows (via the RAS# signals) and columns  
   (via the CAS# signals).  Each RAS# signal in use by the memory  
   subsystem goes to a different row of memory.  The 82450KX PCIset  
   supports a maximum of 4 rows of memory (numbered 0 through 3), and  
   the 82450GX PCIset supports a maximum of 8 rows of memory  
   (numbered 0 through 7). 
 
   Most DRAM comes in one of three varieties.   
 
   A SIMM (Single Inline Memory Module) has a 32-bit data path to  
   its memory.   
 
   Double-sided SIMMs (also known as double-row SIMMs) also use a  
   32-bit data path, but are addressed using two RAS# signals.  These 
   contain two rows of memory.  Since the data path of the 82450KX/GX  
   PCIset is 64-bits wide, both types of SIMMs must be used in pairs.   
 
   A DIMM (Dual Inline Memory Module) uses a 64-bit data path,  
   therefore, single DIMMs can be used in a system.  All SIMMs or  
   DIMMs in a single row of memory must have the same amount of DRAM  
   (differently-sized DRAM modules in the same row will both default  
   to the size of the smaller module). 
 
   Memory interleaving is a technique used in memory subsystem  
   architectures to increase the throughput of memory accesses,  
   by decreasing memory burst latency.  The burst rate increases  
   with each additional interleave of memory (up to 4).  The 82450KX  
   PCIset supports 1:1 and 2:1 interleaving (burst latencies of 4  
   clocks and 2 clocks, respectively).  The 82450GX PCIset supports  
   4:1 interleaving (burst latency of 1 clock) in addition to 1:1 and 
   2:1 interleaving.  When memory is interleaved, a pair of  
   single-sided SIMMs or a single DIMM is also called an interleave 
   increment. For example: 
 
   * Two 8MB SIMMs or one 16MB DIMM comprise an interleave increment  
     of 16MB. 
 
   * Four 16MB SIMMs or two 32MB DIMMs comprise two interleave  
     increments of 32MB each.  In 1:1 interleaving, these interleave  
     increments are in two different rows.  In 2:1 interleaving, they  
     are in the same row. 
 
   Since double-sided SIMMs straddle two rows of memory, a pair of  
   these DRAM modules create two rows with interleave increments of  
   equal size.  For example: 
 
   * Two 16MB double-sided SIMMs comprise two rows of 16MB of memory  
     each, with one 16MB interleave increment per row.  The interleaving 
     is 1:1 in this case. 
 
   * Four 32MB double-sided SIMMs can comprise two rows of 64MB each,  
     with two interleave increments of 32MB in each row.  The interleaving 
     is 2:1 in this case. 
 
   * Four 32MB double-sided SIMMs can also comprise four rows of 32MB 
     each, with one 32MB interleave increment per row.  The interleaving 
     is 1:1 in this case. 
 
   Each interleave increment in a single row will automatically be  
   configured to be the same size.  However, if two or more rows of  
   memory are used in a system, a single interleave of memory may  
   have differently-sized interleave increments (unless the two rows 
   are formed by double-sided SIMMs).  This is the problematic situation. 
 
   If some DRAM module sizes are mixed together, some 82450GX  
   PCIset-based systems may corrupt user or system data, resulting in 
   incorrect calculations and/or system failure. 


ACTION 
 
   Do NOT mix DIMM sizes in the same system.
 
 
NOTES 
 
   The above information is provided by Intel Corp. and is used by 
   permission.  

   The above information is not of a confidential nature. 
 
 
TAN N/A 
 
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